FAST
2011
12 years 7 months ago
2011
Multi-tier systems that combine SSDs with SAS/FC and/or SATA disks mitigate the capital cost burden of SSDs, while benefiting from their superior I/O performance per unit cost an...
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
RTAS
2003
IEEE
13 years 9 months ago
2003
IEEE
Managing energy consumption has become vitally important to battery operated portable and embedded systems. A dynamic voltage scaling (DVS) technique reduces the processor’s dyn...
ASPDAC
2004
ACM
13 years 9 months ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary interna...
SAMOS
2007
Springer
13 years 10 months ago
2007
Springer
When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
ICCD
2001
IEEE
14 years 1 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
OSDI
2008
ACM
14 years 4 months ago
2008
ACM
Dynamic power management in enterprise environments requires an understanding of the relationship between resource utilization and system-level power consumption. Power models bas...
VLSID
2006
IEEE
14 years 4 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...