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2011
8 years 3 months ago
Cost Effective Storage using Extent Based Dynamic Tiering
Multi-tier systems that combine SSDs with SAS/FC and/or SATA disks mitigate the capital cost burden of SSDs, while benefiting from their superior I/O performance per unit cost an...
Jorge Guerra, Himabindu Pucha, Joseph S. Glider, W...
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
9 years 3 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
RTAS
2003
IEEE
9 years 5 months ago
Collaborative Operating System and Compiler Power Management for Real-Time Applications
Managing energy consumption has become vitally important to battery operated portable and embedded systems. A dynamic voltage scaling (DVS) technique reduces the processor’s dyn...
Nevine AbouGhazaleh, Daniel Mossé, Bruce R....
ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
9 years 5 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf
ASPDAC
2006
ACM
92views Hardware» more  ASPDAC 2006»
9 years 6 months ago
Double edge triggered Feedback Flip-Flop in sub 100NM technology
In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary interna...
S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali...
SAMOS
2007
Springer
9 years 6 months ago
Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors
When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however...
Pepijn J. de Langen, Ben H. H. Juurlink
ICCAD
2003
IEEE
221views Hardware» more  ICCAD 2003»
9 years 9 months ago
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
Le Yan, Jiong Luo, Niraj K. Jha
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
9 years 9 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
OSDI
2008
ACM
10 years 12 days ago
A Comparison of High-Level Full-System Power Models
Dynamic power management in enterprise environments requires an understanding of the relationship between resource utilization and system-level power consumption. Power models bas...
Suzanne Rivoire, Parthasarathy Ranganathan, Christ...
VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
10 years 14 days ago
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
Koushik Maharatna, Alfonso Troya, Milos Krstic, Ec...
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