Sciweavers

SLIP
2004
ACM
13 years 9 months ago
Interconnect-power dissipation in a microprocessor
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the...
Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum ...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
13 years 10 months ago
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
Anshuman Chandra, Felix Ng, Rohit Kapur
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
14 years 16 days ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 4 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...