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ETS
2007
IEEE
128views Hardware» more  ETS 2007»
13 years 6 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
DAC
2006
ACM
13 years 6 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
CF
2005
ACM
13 years 6 months ago
On the energy-efficiency of speculative hardware
Microprocessor trends are moving towards wider architectures and more aggressive speculation. With the increasing transistor budgets, energy consumption has become a critical desi...
Nana B. Sam, Martin Burtscher
CASES
2005
ACM
13 years 6 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
CASES
2005
ACM
13 years 6 months ago
Intra-task scenario-aware voltage scheduling
Modern embedded applications usually have real-time constraints and they have requirements for low energy consumption. At system level, intra-task dynamic voltage scaling (DVS) is...
Stefan Valentin Gheorghita, Twan Basten, Henk Corp...
CBSE
2008
Springer
13 years 6 months ago
Component-Level Energy Consumption Estimation for Distributed Java-Based Software Systems
Efficiency with respect to energy consumption has increasingly been recognized as an important quality attribute for distributed software systems in embedded and pervasive environm...
Chiyoung Seo, Sam Malek, Nenad Medvidovic
ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
13 years 6 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
APNOMS
2008
Springer
13 years 6 months ago
A Logical Group Formation and Management Mechanism Using RSSI for Wireless Sensor Networks
Abstract. Wireless sensor network is a suitable technology for ubiquitous environment. However, in WSN, as the network size grows larger, overheads such as flooding, calculation an...
Jihyuk Heo, Jin Ho Kim, Choong Seon Hong
ACMACE
2008
ACM
13 years 6 months ago
Evaluation of a pervasive game for domestic energy engagement among teenagers
In this paper, we present Power Agent - a pervasive game designed to encourage teenagers and their families to reduce energy consumption in the home. The idea behind this mobile p...
Anton Gustafsson, Magnus Bång
NSDI
2008
13 years 6 months ago
Reducing Network Energy Consumption via Sleeping and Rate-Adaptation
We present the design and evaluation of two forms of power management schemes that reduce the energy consumption of networks. The first is based on putting network components to s...
Sergiu Nedevschi, Lucian Popa, Gianluca Iannaccone...