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CODES
2009
IEEE
9 years 29 days ago
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
Mohammad Ali Ghodrat, Tony Givargis
CASES
2005
ACM
9 years 1 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
RTSS
2005
IEEE
9 years 5 months ago
A Hybrid Static/Dynamic DVS Scheduling for Real-Time Systems with (m, k)-Guarantee
Energy reduction is critical to increase the mobility and to extend the mission period in the development of today’s pervasive computing systems. On the other hand, however, ene...
Linwei Niu, Gang Quan
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
9 years 5 months ago
Workload prediction and dynamic voltage scaling for MPEG decoding
– In this paper we present three efficient DVS techniques for an MPEG decoder. Their energy reduction is comparable to that of the optimal solution. A workload prediction model i...
Ying Tan, Parth Malani, Qinru Qiu, Qing Wu
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