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SIGSOFT
2010
ACM
8 years 11 months ago
Differential static analysis: opportunities, applications, and challenges
It is widely believed that program analysis can be more closely targeted to the needs of programmers if the program is accompanied by further redundant documentation. This may inc...
Shuvendu K. Lahiri, Kapil Vaswani, C. A. R. Hoare
FMCAD
2008
Springer
9 years 2 months ago
Recording Synthesis History for Sequential Verification
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...
Alan Mishchenko, Robert K. Brayton
DSD
2007
IEEE
117views Hardware» more  DSD 2007»
9 years 5 months ago
On Complexity of Internal and External Equivalence Checking
We compare the complexity of "internal" and "external" equivalence checking. The former is meant for proving the correctness of a synthesis transformation by w...
Eugene Goldberg, Kanupriya Gulati
DAC
2007
ACM
9 years 5 months ago
Memory Modeling in ESL-RTL Equivalence Checking
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Alfred Kölbl, Jerry R. Burch, Carl Pixley
DAC
2007
ACM
9 years 5 months ago
Design for Verification in System-level Models and RTL
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often...
Anmol Mathur, Venkat Krishnaswamy
ASPDAC
2009
ACM
144views Hardware» more  ASPDAC 2009»
9 years 6 months ago
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis
Iterative retiming and resynthesis is a powerful way to optimize sequential circuits but its massive adoption has been hampered by the hardness of verification. This paper tackle...
Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
9 years 6 months ago
Optimizing equivalence checking for behavioral synthesis
Abstract—Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checki...
Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang
MEMOCODE
2008
IEEE
9 years 7 months ago
Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation Systems
Equivalence checking is a classical verification method determining if a finite-state concurrent system (protocol) satisfies its desired external behaviour (service) by compari...
Radu Mateescu, Emilie Oudot
GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
9 years 7 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
ICCAD
2007
IEEE
109views Hardware» more  ICCAD 2007»
9 years 10 months ago
Inductive equivalence checking under retiming and resynthesis
Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification c...
Jie-Hong Roland Jiang, Wei-Lun Hung
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