Sciweavers

Share
ERSA
2009
107views Hardware» more  ERSA 2009»
9 years 9 months ago
Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures
For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigur...
Kenneth C. Rovers, Marcel D. van de Burgwal, Jan K...
ERSA
2009
129views Hardware» more  ERSA 2009»
9 years 9 months ago
Data path Configuration Time Reduction for Run-time Reconfigurable Systems
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...
ERSA
2009
387views Hardware» more  ERSA 2009»
9 years 9 months ago
Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices
Abstract-- The paper presents the implementation of nonlinear least-squares regression in a Field Programmable Gate Array (FPGA) device. The implemented algorithm is very performan...
Andrea Abba, Antonio Manenti, Andrea Suardi, Angel...
ERSA
2009
147views Hardware» more  ERSA 2009»
9 years 9 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
ERSA
2009
91views Hardware» more  ERSA 2009»
9 years 9 months ago
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors
Configuration with Self-configured Data Path (CSDP) is a high speed configuration data loading method for Dynamically Reconfigurable Processors (DRPs). By using a prepared configu...
Toru Sano, Yoshiki Saito, Hideharu Amano
ERSA
2009
149views Hardware» more  ERSA 2009»
9 years 9 months ago
Harnessing Human Computation Cycles for the FPGA Placement Problem
Harnessing human computation is an approach to find problem solutions. In this paper, we investigate harnessing this human computation for a Field Programmable Gate Array (FPGA) p...
Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit S...
ERSA
2009
131views Hardware» more  ERSA 2009»
9 years 9 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
ERSA
2009
109views Hardware» more  ERSA 2009»
9 years 9 months ago
An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core Processors
An increasing number of embedded system solutions in space, military, and consumer electronics applications rely on processor cores inside reconfigurable logic devices. Ensuring da...
Austin Rogers, Aleksandar Milenkovic
ERSA
2009
146views Hardware» more  ERSA 2009»
9 years 9 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...
books