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EURODAC
1994
IEEE
149views VHDL» more  EURODAC 1994»
8 years 7 months ago
A flexible access control mechanism for CAD frameworks
A. J. van der Hoeven, K. Olav ten Bosch, Rene van ...
EURODAC
1994
IEEE
110views VHDL» more  EURODAC 1994»
8 years 7 months ago
An experimental analysis of the effectiveness of the circular self-test path technique
Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
8 years 7 months ago
System-Level Modeling and Verification: a Comprehensive Design Methodology
Paolo Camurati, Fulvio Corno, Paolo Prinetto, Cath...
EURODAC
1994
IEEE
115views VHDL» more  EURODAC 1994»
8 years 8 months ago
A method for partitioning UNITY language in hardware and software
In this paper we introduce a method to partition UNITY system speci cations into software and hardware parts. This method considers di erent design possibilities and de nes cost f...
Xun Xiong, Edna Barros, Wolfgang Rosenstiel
EURODAC
1994
IEEE
110views VHDL» more  EURODAC 1994»
8 years 8 months ago
Symbolic exploration of large circuits with enhanced forward/backward traversals
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
EURODAC
1994
IEEE
118views VHDL» more  EURODAC 1994»
8 years 8 months ago
A new knowledge-based design manager assistant for CAD frameworks
In this paper we introduce a new knowledgebased method for planning and managing the VLSI design process, based on prediction and advice, that minimizes search in a wide design sp...
Félix Moreno, Juan M. Meneses
EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
8 years 8 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
8 years 8 months ago
A portable and extendible testbed for distributed logic simulation
A exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
Peter Luksch
EURODAC
1994
IEEE
138views VHDL» more  EURODAC 1994»
8 years 8 months ago
A VHDL-based bus model for multi-PCB system design
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....
Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuo...
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