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EURODAC
1994
IEEE
123views VHDL» more  EURODAC 1994»
11 years 3 months ago
Testing redundant asynchronous circuits by variable phase splitting
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
Luciano Lavagno, Antonio Lioy, Michael Kishinevsky
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
11 years 3 months ago
Design automation of self checking circuits
In this paper we explain the steps of the CAD tools developed for self checking circuits. The CAD tools developed are used to design Strongly Fault Secure, Strongly Code Disjoint ...
Sayed Mohammad Kia, Sri Parameswaran
EURODAC
1994
IEEE
115views VHDL» more  EURODAC 1994»
11 years 3 months ago
A tightly coupled approach to design and data management
Flávio Rech Wagner, Lia Goldstein Golendzin...
EURODAC
1994
IEEE
113views VHDL» more  EURODAC 1994»
11 years 3 months ago
Formal verification of pipeline conflicts in RISC processors
We outline a general methodology for the formal verification of pipeline conflicts in RISC cores. The different kinds of conflicts that can occur due to the simultaneous execution...
Ramayya Kumar, Sofiène Tahar
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
11 years 3 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
11 years 3 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
EURODAC
1994
IEEE
163views VHDL» more  EURODAC 1994»
11 years 3 months ago
VHDL and cyclic corrector codes
Cyclic corrector codes, or "block codes", are often used in telecommunications systems. To facilitate the design of coding/decoding circuits using this type of code, we ...
France Mendez
EURODAC
1994
IEEE
118views VHDL» more  EURODAC 1994»
11 years 3 months ago
The semantics of behavioral VHDL '93 descriptions
We present a rigorous but transparent semantic de nition of VHDL'93 covering the complete signal behavior and time model including the various wait statements and signal assi...
Wolfgang Müller 0003, Egon Börger, Uwe G...
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
11 years 3 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
EURODAC
1994
IEEE
116views VHDL» more  EURODAC 1994»
11 years 3 months ago
A performance evaluator for parameterized ASIC architectures
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
Jie Gong, Daniel D. Gajski, Alex Nicolau
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