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EURODAC
1994
IEEE
140views VHDL» more  EURODAC 1994»
11 years 4 months ago
GSA: scheduling and allocation using genetic algorithm
This paper describes a unique approach to scheduling and allocation problem in high-level synthesis using genetic algorithm (GA). This approach is dierent from a previous attempt ...
Ali Shahid, Muhammad S. T. Benten, Sadiq M. Sait
EURODAC
1994
IEEE
124views VHDL» more  EURODAC 1994»
11 years 4 months ago
Automotive databus simulation using VHDL
developed and standardised, for example CAN[1][2], J1850[3]. THE ELECTRONIC VEHICLE TODAYVHDL has been used to develop a simulator for automotive databus networks. This is a design...
Karen Hale
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
11 years 4 months ago
Generating VHDL models from natural language descriptions
This paper describes two approaches to the automatic generation of behavioral VHDL models from descriptions written in natural language. Both approaches are based on a modeling st...
Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik...
EURODAC
1994
IEEE
377views VHDL» more  EURODAC 1994»
11 years 4 months ago
VHDL switch level fault simulation
Christopher A. Ryan, Joseph G. Tront
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
11 years 4 months ago
A general state graph transformation framework for asynchronous synthesis
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekberg...
EURODAC
1994
IEEE
139views VHDL» more  EURODAC 1994»
11 years 4 months ago
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
: This paper presents an approach to high-level synthesis which is based upon a 0/1 integer programming model. In contrast to other approaches, this model allows solving all three ...
Birger Landwehr, Peter Marwedel, Rainer Dömer
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
11 years 4 months ago
Parallel algorithms for the simulation of lossy transmission lines
The simulation of lossy transmission lines in the time domain is a very time consuming task. It requires numerical convolutions and the solution of linear and nonlinear equation s...
W. Rissiek, O. Rethmeier, H. Holzheuer
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
11 years 4 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
EURODAC
1994
IEEE
221views VHDL» more  EURODAC 1994»
11 years 4 months ago
Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools
payload. The current recommendations include SDH as the physical layer transmission standard. It is defined the BISDN user network interface (UNI) SDH-based at 155.52 Mbit/s, but t...
Juan Carlos Calderón, Enric Corominas, Jos&...
EURODAC
1994
IEEE
112views VHDL» more  EURODAC 1994»
11 years 4 months ago
The use of semantic information for control of a complex routing tool
To handle increasingly complex design data, CAD tools are becoming more specialised and complex and hence, more difficult to use. This paper describes an interactive system that h...
Michael Brown, Nick Filer, Zahir Moosa
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