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EURODAC
1994
IEEE
146views VHDL» more  EURODAC 1994»
11 years 3 months ago
Efficient algorithms for interface timing verification
Ti-Yen Yen, Wayne Wolf, Albert E. Casavant, Alex I...
EURODAC
1994
IEEE
105views VHDL» more  EURODAC 1994»
11 years 3 months ago
On Design Rule Correct Maze Routing
This paper addresses the problem of design rule correct routing, i.e. the avoidance of illegal wiring patterns during routing. These illegal wiring patterns are due to the set of ...
Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen...
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
11 years 3 months ago
Synthesis of Self-Testable Controllers
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...
Sybille Hellebrand, Hans-Joachim Wunderlich
EURODAC
1994
IEEE
106views VHDL» more  EURODAC 1994»
11 years 3 months ago
Scheduling with Environmental Constraints based on Automata Representations
Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizi...
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
11 years 3 months ago
A Generalized Signal Transition Graph Model for Specification of Complex Interfaces
This paper introduces a new Generalized Signal Transition Graph model for specifying complex mixed asynchronous/synchronouscircuits, as found in system-level interfaces. Our goal h...
Peter Vanbekbergen, Chantal Ykman-Couvreur, Bill L...
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
11 years 3 months ago
Logic and Fault Simulation by Cellular Automata
Yih-Lang Li, Cheng-Wen Wu
EURODAC
1994
IEEE
112views VHDL» more  EURODAC 1994»
11 years 3 months ago
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions
Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Ma...
EURODAC
1994
IEEE
149views VHDL» more  EURODAC 1994»
11 years 3 months ago
A Graphical Approach to Analogue Behavioural Modelling
In order to master the growing complexity of analogue electronic systems, modelling and simulation of analogue hardware at various levels is absolutely necessary. This paper prese...
Vincent Moser, Pascal Nussbaum, Hans Peter Amann, ...
EURODAC
1994
IEEE
94views VHDL» more  EURODAC 1994»
11 years 3 months ago
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...
Richard McGowen, F. Joel Ferguson
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