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EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
9 years 10 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...
EURODAC
1995
IEEE
142views VHDL» more  EURODAC 1995»
9 years 10 months ago
Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics
Because it costs to solve ElectroMagnetic Compatibility (EMC) problems late in the development process, new methods have to predict radiated electromagnetic emissions at the desig...
E. Leroux, Flavio G. Canavero, G. Vecchi
EURODAC
1995
IEEE
112views VHDL» more  EURODAC 1995»
9 years 10 months ago
On implementation choices for iterative improvement partitioning algorithms
Iterative improvement partitioning algorithms such as the FM algorithm of Fiduccia and Mattheyses 8 , the algorithm of Krishnamurthy 13 , and Sanchis's extensions of these al...
Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
9 years 10 months ago
Use of embedded scheduling to compile VHDL for effective parallel simulation
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
John Willis, Zhiyuan Li, Tsang-Puu Lin
EURODAC
1995
IEEE
152views VHDL» more  EURODAC 1995»
9 years 10 months ago
Information model of a compound graph representation for system and architecture level design
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
Peter Conradi
EURODAC
1995
IEEE
138views VHDL» more  EURODAC 1995»
9 years 10 months ago
Reduced design time by load distribution with CAD framework methodology information
This paper is focused on reducing the design time in a CAD framework environment by the optimal use of resources. A user-transparent load distribution system (Framework based LOad...
Jürgen Schubert, Arno Kunzmann, Wolfgang Rose...
EURODAC
1995
IEEE
202views VHDL» more  EURODAC 1995»
9 years 10 months ago
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
Distributed systems are becoming a popular way of implementing many embedded computing applications, automotive control being a common and important example. Such embedded systems...
Santhanam Srinivasan, Niraj K. Jha
EURODAC
1995
IEEE
127views VHDL» more  EURODAC 1995»
9 years 10 months ago
Layout synthesis for datapath designs
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charle...
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