EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
In this paper, we present a new model for concurrency control that supports cooperation of design tools and designers in a design environment. We capture characteristic access and...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level descripti...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We present a system for the formal veri cation of processors which combines a computer algebra simpli cation tool with an object-oriented approach. It has been successfully used f...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
The presented fault model uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including faults that connect more than two nets...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper describes the features and design methodology of MIDA, a MPEG1 integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL desc...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
An important system design task is the partitioning of system functionality for implementation among multiple system components, including partitions among hardware and software c...