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ETS
2009
IEEE
98views Hardware» more  ETS 2009»
9 years 1 months ago
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
Stephan Eggersglüß, Rolf Drechsler
ICCAD
2010
IEEE
186views Hardware» more  ICCAD 2010»
9 years 1 months ago
Application-Aware diagnosis of runtime hardware faults
Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Currently available online t...
Andrea Pellegrini, Valeria Bertacco
TCAD
2002
106views more  TCAD 2002»
9 years 3 months ago
Design of hierarchical cellular automata for on-chip test pattern generator
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...
Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaud...
ET
1998
52views more  ET 1998»
9 years 3 months ago
Scalable Test Generators for High-Speed Datapath Circuits
This paper explores the design of efficient test sets and test-pattern generators for online BIST. The target applications are high-performance, scalable datapath circuits for whi...
Hussain Al-Asaad, John P. Hayes, Brian T. Murray
ET
2002
84views more  ET 2002»
9 years 3 months ago
Hardware Generation of Random Single Input Change Test Sequences
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
René David, Patrick Girard, Christian Landr...
INTEGRATION
2006
102views more  INTEGRATION 2006»
9 years 3 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
FTCS
1993
94views more  FTCS 1993»
9 years 5 months ago
Balance Testing of Logic Circuits
We present a new test response compression method called cumulative balance testing (CBT)that extends both balance testing and accumulatorcompression testing. CBT uses an accumulat...
Krishnendu Chakrabarty, John P. Hayes
FORTE
2000
9 years 5 months ago
On Test Derivation from Partial Specifications
The paper addresses the problem of test derivation from partially defined specifications. A specification is modeled by an Input/Output FSM such that transitions from some states ...
Alexandre Petrenko, Nina Yevtushenko
DSD
2005
IEEE
96views Hardware» more  DSD 2005»
9 years 5 months ago
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
Peter Filter, Hana Kubatova
VTS
1995
IEEE
100views Hardware» more  VTS 1995»
9 years 7 months ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey
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