ITC
1995
IEEE
13 years 8 months ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
ITC
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
ICES
2000
Springer
13 years 8 months ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
ICCAD
1990
IEEE
13 years 8 months ago
1990
IEEE
Partial detectability profiles are formed by randomly sampling each fault's detectability and are used in estimating the fault coverage of random input test vectors on combin...
ITC
1994
IEEE
13 years 8 months ago
1994
IEEE
For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavi...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
ITC
1996
IEEE
13 years 8 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
ASPDAC
1998
ACM
13 years 8 months ago
1998
ACM
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...