ISMVL
2007
IEEE
13 years 10 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
DATE
2008
IEEE
13 years 10 months ago
2008
IEEE
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
FDTC
2009
Springer
13 years 11 months ago
2009
Springer
—Fault injection attacks are a powerful tool to exploit implementative weaknesses of robust cryptographic algorithms. The faults induced during the computation of the cryptograph...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
- We describe a preprocessing step to fault diagnosis of an observed response obtained from a faulty chip. In this step, a fault model for diagnosing the observed response is selec...
CARDIS
2010
Springer
13 years 11 months ago
2010
Springer
At ACISP 2004, Giraud and Knudsen presented the first fault analysis of DSA, ECDSA, XTR-DSA, Schnorr and ElGamal signatures schemes that considered faults affecting one byte. The...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...