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DAC
2010
ACM
9 years 7 months ago
Efficient fault simulation on many-core processors
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
Michael A. Kochte, Marcel Schaal, Hans-Joachim Wun...
ICCAD
1998
IEEE
117views Hardware» more  ICCAD 1998»
9 years 8 months ago
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
Junwei Hou, Abhijit Chatterjee
ITC
1999
IEEE
103views Hardware» more  ITC 1999»
9 years 8 months ago
Resistive bridge fault modeling, simulation and test generation
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
Vijay R. Sar-Dessai, D. M. H. Walker
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
9 years 8 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
DELTA
2002
IEEE
9 years 8 months ago
Multi-Level Fault Simulation of Digital Systems on Decision Diagrams
A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-...
Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
9 years 8 months ago
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
A uniļ¬ed approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the set...
Michael Pronath, Helmut E. Graeb, Kurt Antreich
FPL
2004
Springer
94views Hardware» more  FPL 2004»
9 years 9 months ago
Evaluating Fault Emulation on FPGA
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, K...
EDCC
2005
Springer
9 years 9 months ago
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs
Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSB...
Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jut...
DSD
2005
IEEE
105views Hardware» more  DSD 2005»
9 years 9 months ago
Improved Fault Emulation for Synchronous Sequential Circuits
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, R...
DFT
2007
IEEE
109views VLSI» more  DFT 2007»
9 years 10 months ago
Safety Evaluation of NanoFabrics
Chemically Assembled Electronic Nanotechnology is a promising alternative to CMOS fabrication. In particular, the nanoFabric has proven to be a viable solution for implementing di...
Michelangelo Grosso, Maurizio Rebaudengo, Matteo S...
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