FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
In this paper we introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. Our performance estimate shows that ou...
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper describes a powerful, scalable, reconfigurable computer called the PARTS engine. The PARTS engine consists of 16 Xilinx 4025 FPGAs, and 16 one-megabyte SRAMs. The FPGAs...
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we descri...
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
The Wormhole Run-Time Reconfiguration (RTR) computing paradigm is a method for creating high performance computational pipelines. The scalability, distributed control and data pow...
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
Square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simpl...
FCCM
1997
IEEE
13 years 8 months ago
1997
IEEE
The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut o...