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FCCM
2006
IEEE
170views VLSI» more  FCCM 2006»
9 years 6 months ago
An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems
The Apriori algorithm is a fundamental correlation-based data mining kernel used in a variety of fields. The innovation in this paper is a highly parallel custom architecture impl...
Zachary K. Baker, Viktor K. Prasanna
FCCM
2006
IEEE
201views VLSI» more  FCCM 2006»
9 years 6 months ago
Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers
With advances in reconfigurable hardware, especially field-programmable gate arrays (FPGAs), it has become possible to use reconfigurable hardware to accelerate complex applicatio...
Ronald Scrofano, Maya Gokhale, Frans Trouw, Viktor...
FCCM
2006
IEEE
138views VLSI» more  FCCM 2006»
9 years 6 months ago
Efficient Hardware Generation of Random Variates with Arbitrary Distributions
This paper presents a technique for efficiently generating random numbers from a given probability distribution. This is achieved by using a generic hardware architecture, which t...
David B. Thomas, Wayne Luk
FCCM
2006
IEEE
117views VLSI» more  FCCM 2006»
9 years 8 months ago
A Scalable Hybrid Regular Expression Pattern Matcher
James Moscola, Young H. Cho, John W. Lockwood
FCCM
2006
IEEE
136views VLSI» more  FCCM 2006»
9 years 8 months ago
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs
Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bel...
FCCM
2006
IEEE
106views VLSI» more  FCCM 2006»
9 years 8 months ago
Scalable Hardware Architecture for Real-Time Dynamic Programming Applications
Abstract— This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of a...
Brad Matthews, Itamar Elhanany
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
9 years 8 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
FCCM
2006
IEEE
121views VLSI» more  FCCM 2006»
9 years 8 months ago
COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking
Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfei...
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
9 years 8 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
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