Sciweavers

FCCM
2008
IEEE
112views VLSI» more  FCCM 2008»
13 years 10 months ago
Power-Aware and Branch-Aware Word-Length Optimization
Power reduction is becoming more important as circuit size increases. This paper presents a tool called PowerCutter which employs accuracy-guaranteed word-length optimization to r...
William G. Osborne, José Gabriel F. Coutinh...
FCCM
2008
IEEE
118views VLSI» more  FCCM 2008»
13 years 10 months ago
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
François Charot, Christophe Wolinski, Nicol...
FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
13 years 10 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....
FCCM
2008
IEEE
177views VLSI» more  FCCM 2008»
13 years 10 months ago
Hardware Scripting in Gel
—Gel is a hardware description language that enables quick scripting of high level designs and can be easily extended to new design patterns. It is expression oriented and extrem...
Jonathan Bachrach, Dany Qumsiyeh, Mark Tobenkin
FCCM
2008
IEEE
128views VLSI» more  FCCM 2008»
13 years 10 months ago
Kiwi: Synthesis of FPGA Circuits from Parallel Programs
David J. Greaves, Satnam Singh
FCCM
2008
IEEE
115views VLSI» more  FCCM 2008»
13 years 10 months ago
Simultaneous Retiming and Placement for Pipelined Netlists
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architecture...
Kenneth Eguro, Scott Hauck
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
13 years 10 months ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
FCCM
2008
IEEE
162views VLSI» more  FCCM 2008»
13 years 10 months ago
Multiobjective Optimization of FPGA-Based Medical Image Registration
With a multitude of technological innovations, one emerging trend in image processing, and medical image processing, in particular, is custom hardware implementation of computatio...
Omkar Dandekar, William Plishker, Shuvra S. Bhatta...
FCCM
2008
IEEE
121views VLSI» more  FCCM 2008»
13 years 10 months ago
FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography
Jack Coyne, David Cyganski, R. James Duckworth
FCCM
2008
IEEE
205views VLSI» more  FCCM 2008»
13 years 10 months ago
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation
The recent turmoil in global credit markets has demonstrated the need for advanced modelling of credit risk, which can take into account the effects of changing economic condition...
David B. Thomas, Wayne Luk