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ISCAPDCS
2001
9 years 1 months ago
A Multiple Blocks Fetch Engine for High Performance Superscalar Processors
The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one bra...
Yung-Chung Wu, Jong-Jiann Shieh
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
9 years 3 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
ASSETS
2006
ACM
9 years 3 months ago
Where's my stuff?: design and evaluation of a mobile system for locating lost items for the visually impaired
Finding lost items is a common problem for the visually impaired and is something that computing technology can help alleviate. In this paper, we present the design and evaluation...
Julie A. Kientz, Shwetak N. Patel, Arwa Z. Tyebkha...
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
9 years 3 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
9 years 3 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
ICS
1999
Tsinghua U.
9 years 4 months ago
Software trace cache
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...
ICPP
2002
IEEE
9 years 5 months ago
Out-of-Order Instruction Fetch Using Multiple Sequencers
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
Paramjit S. Oberoi, Gurindar S. Sohi
ISLPED
2005
ACM
101views Hardware» more  ISLPED 2005»
9 years 5 months ago
Energy-aware fetch mechanism: trace cache and BTB customization
1 A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on pr...
Daniel Chaver, Miguel A. Rojas, Luis Piñuel...
APCSAC
2005
IEEE
9 years 5 months ago
Energy-Effective Instruction Fetch Unit for Wide Issue Processors
Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such ...
Juan L. Aragón, Alexander V. Veidenbaum
ISCA
2008
IEEE
150views Hardware» more  ISCA 2008»
9 years 6 months ago
Fetch-Criticality Reduction through Control Independence
Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from th...
Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matth...
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