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    ISCA
    1995
    IEEE
    110views Hardware» more  ISCA 1995»
    Optimization of Instruction Fetch Mechanisms for High Issue Rates
    13 years 8 months ago
    Optimization of Instruction Fetch Mechanisms for High Issue Rates
    Download  www.eecg.toronto.edu
    Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
    Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
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    ISLPED
    2005
    ACM
    101views Hardware» more  ISLPED 2005»
    Energy-aware fetch mechanism: trace cache and BTB customization
    13 years 10 months ago
    Energy-aware fetch mechanism: trace cache and BTB customization
    Download  www.ece.rochester.edu
    1 A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on pr...
    Daniel Chaver, Miguel A. Rojas, Luis Piñuel...
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