Sciweavers

ICISC
2009
125views Cryptology» more  ICISC 2009»
13 years 1 months ago
Power Analysis of Single-Rail Storage Elements as Used in MDPL
Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...
Amir Moradi, Thomas Eisenbarth, Axel Poschmann, Ch...
CDES
2006
91views Hardware» more  CDES 2006»
13 years 5 months ago
Survey and Evaluation of Low-Power Flip-Flops
We survey a set of flip-flops designed for low power and high performance. We highlight the basic features of these flip-flops and evaluate them based on timing characteristics, po...
Ahmed Sayed, Hussain Al-Asaad
ASPDAC
2006
ACM
96views Hardware» more  ASPDAC 2006»
13 years 7 months ago
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability
Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand...
GLVLSI
2008
IEEE
128views VLSI» more  GLVLSI 2008»
13 years 10 months ago
NBTI-aware flip-flop characterization and design
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
Hamed Abrishami, Safar Hatami, Behnam Amelifard, M...
GLVLSI
2008
IEEE
147views VLSI» more  GLVLSI 2008»
13 years 10 months ago
Statistical timing analysis of flip-flops considering codependent setup and hold times
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
Safar Hatami, Hamed Abrishami, Massoud Pedram
DFT
2009
IEEE
106views VLSI» more  DFT 2009»
13 years 10 months ago
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
13 years 10 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram