Sciweavers

FMCAD
2006
Springer
13 years 8 months ago
Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling
In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent yea...
Florian Pigorsch, Christoph Scholl, Stefan Disch
FMCAD
2006
Springer
13 years 8 months ago
Thorough Checking Revisited
Recent years have seen a proliferation of 3-valued or capturing abstractions of systems, since these enable verifying both universal and existential properties. Reasoning about suc...
Shiva Nejati, Mihaela Gheorghiu, Marsha Chechik
FMCAD
2006
Springer
13 years 8 months ago
Synchronous Elastic Networks
We formally define--at the stream transformer level--a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properti...
Sava Krstic, Jordi Cortadella, Michael Kishinevsky...
FMCAD
2006
Springer
13 years 8 months ago
Finite Instantiations for Integer Difference Logic
The last few years have seen the advent of a new breed of decision procedures for various fragments of first-order logic based on ional abstraction. A lazy satisfiability checker ...
Hyondeuk Kim, Fabio Somenzi
FMCAD
2006
Springer
13 years 8 months ago
Post-reboot Equivalence and Compositional Verification of Hardware
We introduce a finer concept of a Hardware Machine, where the set of post-reboot operation states is explicitly a part of the FSM definition. We formalize an ad-hoc flow of combin...
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Z...
FMCAD
2006
Springer
13 years 8 months ago
Optimizations for LTL Synthesis
We present an approach to automatic synthesis of specifications given in Linear Time Logic. The approach is based on a translation through universal co-B
Barbara Jobstmann, Roderick Bloem
FMCAD
2006
Springer
13 years 8 months ago
Tracking MUSes and Strict Inconsistent Covers
In this paper, a new heuristic-based approach is introduced to extract minimally unsatisfiable subformulas (in short, MUSes) of SAT instances. It is shown that it often outperforms...
Éric Grégoire, Bertrand Mazure, C&ea...
FMCAD
2006
Springer
13 years 8 months ago
Assume-Guarantee Reasoning for Deadlock
Sagar Chaki, Nishant Sinha