Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
RSP
2005
IEEE
162views Control Systems» more  RSP 2005»
10 years 8 months ago
SyCE: An Integrated Environment for System Design in SystemC
We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of Syst...
Rolf Drechsler, Görschwin Fey, Christian Genz...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
11 years 3 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
books