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FTCS
1998
84views more  FTCS 1998»
11 years 6 months ago
On the Use of Formal Techniques for Validation
The traditional use of formal methods has been for the veri cation of algorithms or protocols. Given the high cost and limitations in state space coverage provided by conventional...
Neeraj Suri, Purnendu Sinha
DAC
1994
ACM
11 years 8 months ago
Probabilistic Analysis of Large Finite State Machines
Regarding nite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal veri cation problems. Recently, we ha...
Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fab...
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
11 years 8 months ago
Towards verifying VHDL descriptions of processors
We present a system for the formal veri cation of processors which combines a computer algebra simpli cation tool with an object-oriented approach. It has been successfully used f...
Laurent Arditi, Hélène Collavizza
FAABS
2000
Springer
11 years 9 months ago
From Livingstone to SMV
To ful ll the needs of its deep space exploration program, NASAis actively supporting research and development in autonomy software. However, the reliable and cost-e ective develop...
Charles Pecheur, Reid G. Simmons
DAC
1999
ACM
11 years 9 months ago
Parametric Representations of Boolean Constraints
Abstract We describe the use of parametric representations of Boolean predicates to encode data-space constraints and signi cantly extend the capacity of formal veri cation. The co...
Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
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