ICCD
2000
IEEE
13 years 8 months ago
2000
IEEE
A major obstacle to widespread acceptance of formal verification is the difficulty in using the tools effectively. Although learning the basic syntax and operation of a formal ver...
FSTTCS
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. This paper presents the first formal verification of the RicartAgrawala algorithm [RA81] for distributed mutual exclusion of an arbitrary number of nodes. It uses the Tem...
FMCAD
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. In this paper we describe the formal specification and verification of the efficient algorithm for real-time model checking implemented in the model checker RAVEN. It was...
CHARME
2003
Springer
13 years 8 months ago
2003
Springer
In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complete ...
CHARME
2001
Springer
13 years 8 months ago
2001
Springer
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The ...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
ASIAN
2006
Springer
13 years 8 months ago
2006
Springer
Abstract. It is customary to write performance-critical parts of arithmetic functions in assembly: this enables finely-tuned algorithms that use specialized processor instructions....
HYBRID
2007
Springer
13 years 8 months ago
2007
Springer
Abstract. In this paper, we propose a new approach for formal verification of hybrid systems. To do so, we present a new refinement proof technique, a weak refinement using step in...
GLVLSI
2007
IEEE
13 years 8 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
ASYNC
2007
IEEE
13 years 8 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...