Sciweavers

ICSE
1992
IEEE-ACM
13 years 7 months ago
A Toolbox for the Verification of LOTOS Programs
This paper presents the tools Ald
Jean-Claude Fernandez, Hubert Garavel, Laurent Mou...
DAC
1994
ACM
13 years 7 months ago
HSIS: A BDD-Based Environment for Formal Verification
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now...
Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin...
TPHOL
1999
IEEE
13 years 8 months ago
A Machine-Checked Theory of Floating Point Arithmetic
Abstract. Intel is applying formal verification to various pieces of mathematical software used in Merced, the first implementation of the new IA-64 architecture. This paper discus...
John Harrison
DATE
1999
IEEE
134views Hardware» more  DATE 1999»
13 years 8 months ago
Verifying Imprecisely Working Arithmetic Circuits
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...
Michaela Huhn, Klaus Schneider, Thomas Kropf, Geor...
DATE
2002
IEEE
108views Hardware» more  DATE 2002»
13 years 8 months ago
A Case Study for the Verification of Complex Timed Circuits: IPCMOS
ions + Assume Guarantee + Induction GOAL: Formal verification of the IPCMOS architecture
Marco A. Peña, Jordi Cortadella, Alexander ...
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
13 years 9 months ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
ICCS
2007
Springer
13 years 9 months ago
Equivalent Semantic Translation from Parallel DEVS Models to Time Automata
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...
Shoupeng Han, Kedi Huang
FMCAD
2007
Springer
13 years 9 months ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
13 years 10 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
ICFP
2003
ACM
14 years 3 months ago
A formalization of an Ordered Logical Framework in Hybrid with applications to continuation machines
We report on work in progress devoted to the formalization of an Ordered Logical Framework (OLF) based on a two-level architecture [8] in the Hybrid system. OLF here is a second-or...
Alberto Momigliano, Jeff Polakow