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FPGA
2012
ACM
8views FPGA» more  FPGA 2012»
Accelerator compiler for the VENICE vector processor
1 months 6 days ago
Accelerator compiler for the VENICE vector processor
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Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. ...
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FPGA
2012
ACM
8views FPGA» more  FPGA 2012»
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
1 months 6 days ago
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Download  www.ece.ubc.ca
In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemente...
Yehdhih Ould Mohammed Moctar, Nithin George, Hadi ...
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FPGA
2012
ACM
9views FPGA» more  FPGA 2012»
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
1 months 6 days ago
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
Download  cas.ee.ic.ac.uk
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...
Samuel Bayliss, George A. Constantinides
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FS
2011
38views more  FS 2011»
Gamma expansion of the Heston stochastic volatility model
9 months 3 days ago
Gamma expansion of the Heston stochastic volatility model
Download  www2.gsb.columbia.edu
Abstract We derive an explicit representation of the transitions of the Heston stochastic volatility model and use it for fast and accurate simulation of the model. Of particular i...
Paul Glasserman, Kyoung-Kuk Kim
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FS
2011
48views more  FS 2011»
Asset price bubbles from heterogeneous beliefs about mean reversion rates
9 months 3 days ago
Asset price bubbles from heterogeneous beliefs about mean reversion rates
Download  www.math.nyu.edu
Harrison and Kreps showed in 1978 how the heterogeneity of investor beliefs can drive speculation, leading the price of an asset to exceed its intrinsic value. By focusing on an e...
Xi Chen, Robert V. Kohn
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FPGA
2011
ACM
71views FPGA» more  FPGA 2011»
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
9 months 3 days ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Download  legup.eecg.utoronto.ca
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
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FPGA
2011
ACM
61views FPGA» more  FPGA 2011»
An analytical model relating FPGA architecture parameters to routability
9 months 3 days ago
An analytical model relating FPGA architecture parameters to routability
Download  www.ece.ubc.ca
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch b...
Joydip Das, Steven J. E. Wilton
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FPGA
2011
ACM
62views FPGA» more  FPGA 2011»
CoRAM: an in-fabric memory architecture for FPGA-based computing
9 months 3 days ago
CoRAM: an in-fabric memory architecture for FPGA-based computing
Download  www.ece.cmu.edu
FPGAs have been used in many applications to achieve orders-of-magnitude improvement in absolute performance and energy efficiency relative to conventional microprocessors. Despit...
Eric S. Chung, James C. Hoe, Ken Mai
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FPGA
2011
ACM
74views FPGA» more  FPGA 2011»
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
9 months 3 days ago
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
Download  www.stuffedcow.net
As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This pa...
Henry Wong, Vaughn Betz, Jonathan Rose
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ASPDAC
2011
ACM
63views Hardware» more  ASPDAC 2011»
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
9 months 7 days ago
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
Download  www.kameyama.ecei.tohoku.ac.jp
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...
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