Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
FPGA
1998
ACM
153views FPGA» more  FPGA 1998»
11 years 11 months ago
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
Steven J. E. Wilton
FPGA
1998
ACM
148views FPGA» more  FPGA 1998»
11 years 11 months ago
Optimizations for a Highly Cost-Efficient Programmable Logic Architecture
Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Ch...
FPGA
1998
ACM
140views FPGA» more  FPGA 1998»
11 years 11 months ago
More Wires and Fewer LUTs: A Design Methodology for FPGAs
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
Atsushi Takahara, Toshiaki Miyazaki, Takahiro Muro...
FPGA
1998
ACM
176views FPGA» more  FPGA 1998»
11 years 11 months ago
A Fast Routability-Driven Router for FPGAs
Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute powe...
Jordan S. Swartz, Vaughn Betz, Jonathan Rose
FPGA
1998
ACM
160views FPGA» more  FPGA 1998»
11 years 11 months ago
A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs
In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based eld programmable gate arrays. The algorithm is based on a novel iterative proce...
Peichen Pan, Chih-Chang Lin
FPGA
1998
ACM
180views FPGA» more  FPGA 1998»
11 years 11 months ago
A Novel Predictable Segmented FPGA Routing Architecture
Emil S. Ochotta, Patrick J. Crotty, Charles R. Eri...
FPGA
1998
ACM
125views FPGA» more  FPGA 1998»
11 years 11 months ago
Timing Driven Floorplanning on Programmable Hierarchical Targets
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
S. A. Senouci, A. Amoura, Helena Krupnova, Gabriel...
FPGA
1998
ACM
132views FPGA» more  FPGA 1998»
11 years 11 months ago
Circuit Partitioning with Complex Resource Constraints in FPGAs
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...
Huiqun Liu, Kai Zhu, D. F. Wong
FPGA
1998
ACM
150views FPGA» more  FPGA 1998»
11 years 11 months ago
Efficiently Supporting Fault-Tolerance in FPGAs
John Lach, William H. Mangione-Smith, Miodrag Potk...
FPGA
1998
ACM
152views FPGA» more  FPGA 1998»
11 years 11 months ago
High-Performance Carry Chains for FPGAs
Scott Hauck, Matthew M. Hosler, Thomas W. Fry
books