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FPGA
1999
ACM
122views FPGA» more  FPGA 1999»
11 years 11 months ago
Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System
This paper presents the emulation of an embedded system with hard real time constraints and response times of about 220µs. We show that for such fast reactive systems, the softwa...
Karlheinz Weiß, Thorsten Steckstor, Gernot K...
FPGA
1999
ACM
104views FPGA» more  FPGA 1999»
11 years 11 months ago
Universal Switch Blocks for Three-Dimensional FPGA Design
Guang-Ming Wu, Michael Shyu, Yao-Wen Chang
FPGA
1999
ACM
139views FPGA» more  FPGA 1999»
11 years 11 months ago
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
Yaska Sankar, Jonathan Rose
FPGA
1999
ACM
115views FPGA» more  FPGA 1999»
11 years 11 months ago
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
Alexander Marquardt, Vaughn Betz, Jonathan Rose
FPGA
1999
ACM
137views FPGA» more  FPGA 1999»
11 years 11 months ago
A New High Density and Very Low Cost Reprogrammable FPGA Architecture
Sinan Kaptanoglu, Greg Bakker, Arun Kundu, Ivan Co...
FPGA
1999
ACM
130views FPGA» more  FPGA 1999»
11 years 11 months ago
Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition...
Frank Heile, Andrew Leaver
FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
11 years 11 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
FPGA
1999
ACM
144views FPGA» more  FPGA 1999»
11 years 11 months ago
Configuration Caching Vs Data Caching for Striped FPGAs
Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi
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