FPL
2006
Springer
13 years 8 months ago
2006
Springer
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper ...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
The complexity exhibited by pervasive systems is constantly increasing. Customer electronics devices provide day to day a larger amount of functionalities. A common approach for g...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
In this paper we present the design and implementation of a dynamically reconfigurable system for packet queue scheduling. Two widely accepted queue schedulers have been implement...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
Ripple-carry architectures are the norm in today's reconfigurable fabrics. They are simple, require minimal routing, and are easily formed across arbitrary cells in a fabric....
FPL
2006
Springer
13 years 8 months ago
2006
Springer
: FPGA-based acceleration of molecular dynamics (MD) has been the subject of several recent studies. Here we describe a new non-bonded force computation pipeline implemented on a 2...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
This paper presents an automated partitioning strategy to divide a design into a set of partitions based on design hierarchy information. While the primary objective is to use the...