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FPL
2006
Springer
140views Hardware» more  FPL 2006»
12 years 1 months ago
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
FPL
2006
Springer
99views Hardware» more  FPL 2006»
12 years 1 months ago
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP ...
Daniel Ziener, Stefan Assmus, Jürgen Teich
FPL
2006
Springer
66views Hardware» more  FPL 2006»
12 years 1 months ago
Minimizing Communication Cost for Reconfigurable Slot Modules
We discuss the problem of communication-aware module placement in array-like reconfigurable environments, such as the Erlangen Slot Machine (ESM). Bad placement of modules may deg...
Sándor P. Fekete, Jan van der Veen, Mateusz...
FPL
2006
Springer
158views Hardware» more  FPL 2006»
12 years 1 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...
FPL
2006
Springer
103views Hardware» more  FPL 2006»
12 years 1 months ago
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification
This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols bet...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
FPL
2006
Springer
99views Hardware» more  FPL 2006»
12 years 1 months ago
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs
As manufacturing technology enters the ultra-deep submicron era, wafer yields are destined to drop due to higher occurrence of physical defects on the die. This paper proposes a y...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
FPL
2006
Springer
129views Hardware» more  FPL 2006»
12 years 1 months ago
A Reconfigurable Viterbi Decoder for a Communication Platform
A new large constraint length, soft decision viterbi decoder fabric is presented for deployment using platform based system on chip methodologies. The decoder can be reconfigured ...
Imran Ahmed, Tughrul Arslan
FPL
2006
Springer
147views Hardware» more  FPL 2006»
12 years 1 months ago
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
FPL
2006
Springer
112views Hardware» more  FPL 2006»
12 years 1 months ago
Real-Time Video Pixel Matching
We present an efficient implementation of a state of the art algorithm PixelMatch for matching all pixels within consecutive video frames. The method is of practical interest for ...
Jean-Baptiste Note, Mark Shand, Jean Vuillemin
FPL
2006
Springer
127views Hardware» more  FPL 2006»
12 years 1 months ago
FPGA Vendor Agnostic True Random Number Generator
This paper describes a solution for the generation of true random numbers in a purely digital fashion; making it suitable for any FPGA type, because no FPGA vendor specific featur...
Dries Schellekens, Bart Preneel, Ingrid Verbauwhed...
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