FPL
2007
Springer
13 years 10 months ago
2007
Springer
In this paper, we present a shared instruction and data memory controller for the On-Chip Memory (OCM) bus of the PowerPC embedded in the Virtex-4 chip. The traditional design of ...
FPL
2007
Springer
13 years 10 months ago
2007
Springer
This paper develops a formal model of process migration that describes programs, processes, and the migration of those processes within a migration realm. A migration realm is a g...
FPL
2007
Springer
13 years 10 months ago
2007
Springer
FPL
2007
Springer
13 years 10 months ago
2007
Springer
In this paper we present Minibit+, an approach that optimizes the bit-widths of fixed-point and floating-point designs, while guaranteeing accuracy. Our approach adopts differen...
FPL
2007
Springer
13 years 10 months ago
2007
Springer
FPL
2007
Springer
13 years 10 months ago
2007
Springer
Modern platform FPGAs integrate fine-grained reconfigurable logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodol...
FPL
2007
Springer
13 years 10 months ago
2007
Springer
The reconfigurable mesh is a model for massively parallel computing for which many algorithms with very low complexity have been developed. These algorithms execute cycles of bus...
FPL
2007
Springer
13 years 10 months ago
2007
Springer
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
FPL
2007
Springer
13 years 10 months ago
2007
Springer
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO for placement and routing on ...
FPL
2007
Springer
13 years 10 months ago
2007
Springer
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...