Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
FPL
2008
Springer
138views Hardware» more  FPL 2008»
11 years 3 months ago
An efficient run-time router for connecting modules in FPGAS
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents ...
Jorge Surís, Cameron Patterson, Peter Athan...
FPL
2008
Springer
112views Hardware» more  FPL 2008»
11 years 3 months ago
Fault tolerant methods for reliability in FPGAs
Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing oppor...
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheu...
FPL
2008
Springer
207views Hardware» more  FPL 2008»
11 years 3 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana
FPL
2008
Springer
96views Hardware» more  FPL 2008»
11 years 3 months ago
Towards benchmarking energy efficiency of reconfigurable architectures
Energy research in reconfigurable architectures often involves legacy benchmarks such as the MCNC benchmarks. These benchmarks, however, are not well-suited for assessing energy c...
Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y....
FPL
2008
Springer
141views Hardware» more  FPL 2008»
11 years 3 months ago
An analytical model describing the relationships between logic architecture and FPGA density
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the ...
Andrew Lam, Steven J. E. Wilton, Philip Heng Wai L...
FPL
2008
Springer
104views Hardware» more  FPL 2008»
11 years 3 months ago
A technique for minimizing power during FPGA placement
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...
FPL
2008
Springer
94views Hardware» more  FPL 2008»
11 years 3 months ago
Acceleration of a production rigid molecule docking code
: Modeling the interactions of biological molecules, or docking is critical to both understanding basic life processes and to designing new drugs. Here we describe the FPGA-based a...
Bharat Sukhwani, Martin C. Herbordt
FPL
2008
Springer
105views Hardware» more  FPL 2008»
11 years 3 months ago
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems
A high-speed and secure dynamic partial reconfiguration (DPR) system is realized with AES-GCM that guarantees both confidentiality and authenticity of FPGA bitstreams. In DPR syst...
Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji T...
FPL
2008
Springer
98views Hardware» more  FPL 2008»
11 years 3 months ago
Rapid estimation of power consumption for hybrid FPGAs
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of ...
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Ste...
FPL
2008
Springer
193views Hardware» more  FPL 2008»
11 years 3 months ago
Decimal multiplier on FPGA using embedded binary multipliers
Horácio C. Neto, Mário P. Vés...
books