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FPL
2008
Springer
92views Hardware» more  FPL 2008»
13 years 5 months ago
Parallel hardware objects for dynamically partial reconfiguration
Many of today's software-to-hardware compiler projects try to find dataflow parallelism in a sequential program description and use it to generate parallel running hardware c...
Norbert Abel, Frederik Grüll, Nick Meier, And...
FPL
2008
Springer
86views Hardware» more  FPL 2008»
13 years 5 months ago
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Ha...
FPL
2008
Springer
125views Hardware» more  FPL 2008»
13 years 5 months ago
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconf...
Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dud...
FPL
2008
Springer
110views Hardware» more  FPL 2008»
13 years 5 months ago
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
While there have been many reported implementations of Networks-on-Chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication ...
Matthew Shelburne, Cameron Patterson, Peter Athana...
FPL
2008
Springer
129views Hardware» more  FPL 2008»
13 years 5 months ago
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...
FPL
2008
Springer
154views Hardware» more  FPL 2008»
13 years 5 months ago
Numerical function generators using bilinear interpolation
Two-variable numerical functions are widely used in various applications, such as computer graphics and digital signal processing. Fast and compact hardware implementations are re...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
FPL
2008
Springer
104views Hardware» more  FPL 2008»
13 years 5 months ago
FPGA family composition and effects of specialized blocks
Field-Programmable Gate Arrays (FPGAs) have gained wide acceptance among low- to medium-volume applications. However, there are gaps between FPGA and custom implementations in ter...
Pongstorn Maidee, Nagib Hakim, Kia Bazargan
FPL
2008
Springer
112views Hardware» more  FPL 2008»
13 years 5 months ago
Secure FPGA configuration architecture preventing system downgrade
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a syst...
Benoît Badrignans, Reouven Elbaz, Lionel Tor...
FPL
2008
Springer
124views Hardware» more  FPL 2008»
13 years 5 months ago
Direct sigma-delta modulated signal processing in FPGA
The effectiveness of implementing bit-stream signal processing (BSSP) multiplier circuits in FPGAs, in terms of hardware resources and clock frequency, is presented. In particular...
Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-S...
FPL
2008
Springer
96views Hardware» more  FPL 2008»
13 years 5 months ago
Low-latency high-bandwidth HW/SW communication in a virtual memory environment
Adaptive computers combine conventional software programmable processors with reconfigurable compute units. We present techniques that allow the high-performance realization of de...
Holger Lange, Andreas Koch