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FPL
2009
Springer
98views Hardware» more  FPL 2009»
13 years 9 months ago
Optimal runtime reconfiguration strategies for systolic arrays
Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chambe...
FPL
2009
Springer
152views Hardware» more  FPL 2009»
13 years 9 months ago
Clock gating architectures for FPGA power reduction
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
Safeen Huda, Muntasir Mallick, Jason H. Anderson
FPL
2009
Springer
113views Hardware» more  FPL 2009»
13 years 9 months ago
Clock duplicity for high-precision timestamping in Gigabit Ethernet
Hardware-timestamping is essential for achieving tight synchronization in networking applications. This mechanism is selectively used on few high-cost tailored systems. Actual μP...
Carles Nicolau, Dolors Sala, Enrique Cantó
FPL
2009
Springer
162views Hardware» more  FPL 2009»
13 years 9 months ago
A comparison of FPGA and FPAA technologies for a signal processing application
This paper presents a comparison between two technologies for reconfigurable circuits that are FPGA'se the FPAA's. The comparison is based on a case study of the area of...
Roberto Selow, Heitor S. Lopes, Carlos R. Erig Lim...
FPL
2009
Springer
91views Hardware» more  FPL 2009»
13 years 9 months ago
Large multipliers with fewer DSP blocks
Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier...
Florent de Dinechin, Bogdan Pasca
FPL
2009
Springer
135views Hardware» more  FPL 2009»
13 years 9 months ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
FPL
2009
Springer
166views Hardware» more  FPL 2009»
13 years 9 months ago
Modeling post-techmapping and post-clustering FPGA circuit depth
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookuptable ...
Joydip Das, Steven J. E. Wilton, Philip Heng Wai L...
FPL
2009
Springer
129views Hardware» more  FPL 2009»
13 years 9 months ago
Self-organizing multi-cue fusion for FPGA-based embedded imaging
Self-organization is a natural concept that helps complex systems to adapt themselves autonomically to their environment. In this paper, we present a self-organizing framework for...
Stefan Wildermann, Gregor Walla, Tobias Ziermann, ...
FPL
2009
Springer
172views Hardware» more  FPL 2009»
13 years 9 months ago
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
Nachiket Kapre, André DeHon
FPL
2009
Springer
78views Hardware» more  FPL 2009»
13 years 9 months ago
FPGA-accelerated Information Retrieval: High-efficiency document filtering
Power consumption in data centres is a growing issue as the cost of the power for computation and cooling has become dominant. An emerging challenge is the development of “envir...
Wim Vanderbauwhede, Leif Azzopardi, Mahmoud Moadel...