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FPL
2010
Springer
144views Hardware» more  FPL 2010»
8 years 11 months ago
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs
Andreas Oetken, Stefan Wildermann, Jürgen Tei...
FPL
2010
Springer
111views Hardware» more  FPL 2010»
8 years 11 months ago
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
Abstract--Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rel...
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebe...
FPL
2010
Springer
155views Hardware» more  FPL 2010»
8 years 11 months ago
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Martin Schoeberl, Peter Hilber
FPL
2010
Springer
106views Hardware» more  FPL 2010»
8 years 11 months ago
Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
This paper presents a novel IP core reuse strategy which reduces design time from days to hours for communication circuits such as digital radio receivers. This design productivity...
Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, T...
FPL
2010
Springer
93views Hardware» more  FPL 2010»
8 years 11 months ago
Early Prediction of Hardware Complexity in HLL-to-HDL Translation
Alessandro Cilardo, Paolo Durante, Carmelo Lofiego...
FPL
2010
Springer
174views Hardware» more  FPL 2010»
8 years 11 months ago
ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing
Researchers in embedded and reconfigurable computing are often hindered by a lack of suitable benchmarks with which to accurately evaluate their work. Without a suitable benchmark ...
Daniel W. Chang, Christipher D. Jenkins, Philip C....
FPL
2010
Springer
267views Hardware» more  FPL 2010»
8 years 11 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
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