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JCO
2011
115views more  JCO 2011»
8 years 8 months ago
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
Chen Liao, Shiyan Hu
GRID
2010
Springer
8 years 10 months ago
Dynamic Partitioning of GATE Monte-Carlo Simulations on EGEE
Abstract The EGEE grid offers the necessary infrastructure and resources for reducing the running time of particle tracking Monte-Carlo applications like GATE. However, efforts are...
Sorina Camarasu-Pop, Tristan Glatard, Jakub T. Mos...
TCAD
2008
172views more  TCAD 2008»
9 years 1 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
IEICET
2006
79views more  IEICET 2006»
9 years 1 months ago
System LSI: Challenges and Opportunities
End of CMOS scaling has been discussed in many places since the late 90's. Even if the end of CMOS scaling is irrelevant, it is for sure that we are facing a turning point in...
Tadahiro Kuroda
ANLP
1997
186views more  ANLP 1997»
9 years 2 months ago
Software Infrastructure for Natural Language Processing
We classify and review current approaches to software infrastructure for research, development and delivery of NLP systems. The task is motivated by a discussion of current trends...
Hamish Cunningham, Kevin Humphreys, Robert J. Gaiz...
ISLPED
1997
ACM
94views Hardware» more  ISLPED 1997»
9 years 4 months ago
A gate resizing technique for high reduction in power consumption
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper, we propose a post
Patrick Girard, Christian Landrault, Serge Pravoss...
DAC
1995
ACM
9 years 4 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
VLSID
2010
IEEE
168views VLSI» more  VLSID 2010»
9 years 5 months ago
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the ...
Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
9 years 5 months ago
Optimal latch mapping and retiming within a tree
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
Joel Grodstein, Eric Lehman, Heather Harkness, Her...
ICTAI
1996
IEEE
9 years 5 months ago
GATE: An Environment to Support Research and Development in Natural Language Engineering
We describe a software environment to support research and development in natural language (NL) engineering. This environment
Robert J. Gaizauskas, Hamish Cunningham, Yorick Wi...
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