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ASPDAC
1999
ACM
60views Hardware» more  ASPDAC 1999»
13 years 9 months ago
Timing Optimization of Logic Network Using Gate Duplication
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
Chun-hong Chen, Chi-Ying Tsui
ICCAD
2000
IEEE
84views Hardware» more  ICCAD 2000»
13 years 9 months ago
Timing Driven Gate Duplication: Complexity Issues and Algorithms
This paper addresses the issue of timing driven gate duplication for delay optimization. Gate duplication has been used extensively for cutset minimization but the usefulness in m...
Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh