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ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
12 years 5 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
12 years 6 months ago
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
Saraju P. Mohanty
VLSID
2005
IEEE
224views VLSI» more  VLSID 2005»
13 years 3 days ago
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
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