ISCAS
1999
IEEE
13 years 8 months ago
1999
IEEE
We study the weight dynamics of the floating-gate pFET synapse and the effects of the pFET's gate and drain voltages on these dynamics. We show that we can derive a weight upd...
ISPD
1999
ACM
13 years 8 months ago
1999
ACM
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
ISPD
2003
ACM
13 years 9 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
Speed and Accuracy of programming large floating gate array is limited by precision of current measurement and pulse generator. In this paper a novel floating gate programming m...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires addi...