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    DAC
    1999
    ACM
    179views Computer Architecture» more  DAC 1999»
    A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
    14 years 5 months ago
    A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
    Download  www-ise2.ist.osaka-u.ac.jp
    We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
    Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
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