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ICCAD
2003
IEEE
111views Hardware» more  ICCAD 2003»
10 years 7 months ago
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a given performance qrj,/...
Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. ...
DAC
2004
ACM
10 years 11 months ago
Architecture-level synthesis for automatic interconnect pipelining
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
Jason Cong, Yiping Fan, Zhiru Zhang
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