GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Various coding schemes have been proposed in literature to encode the input signal...
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
Symbolic Model checking is a widely used technique in sequential verification. As the size of the OBDDs and also the computation time depends on the order of the input variables,...
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuous...
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
GLVLSI
2000
IEEE
13 years 8 months ago
2000
IEEE
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...