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GLVLSI
2002
IEEE
98views VLSI» more  GLVLSI 2002»
10 years 4 months ago
Minimizing concurrent test time in SoC's by balancing resource usage
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
10 years 4 months ago
AQUASUN: adaptive window query processing in CAD applications for physical design and verification
Michiel De Wilde, Dirk Stroobandt, Jan Van Campenh...
GLVLSI
2002
IEEE
160views VLSI» more  GLVLSI 2002»
10 years 4 months ago
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations
Spectral techniques have found many applications in computeraided design, including synthesis, verification, and testing. Decision diagram representations permit spectral coeffici...
Whitney J. Townsend, Mitchell A. Thornton, Rolf Dr...
GLVLSI
2002
IEEE
105views VLSI» more  GLVLSI 2002»
10 years 4 months ago
Board-level multiterminal net assignment
The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems. The approach tran...
Xiaoyu Song, William N. N. Hung, Alan Mishchenko, ...
GLVLSI
2002
IEEE
122views VLSI» more  GLVLSI 2002»
10 years 4 months ago
A compact delay model for series-connected MOSFETs
A compact delay model for series connected MOSFETs has been derived. This model enables accurate prediction of worst-case delay of different logic families such as dynamic logic. ...
Kaveh Shakeri, James D. Meindl
GLVLSI
2002
IEEE
103views VLSI» more  GLVLSI 2002»
10 years 4 months ago
Fast and accurate wire delay estimation for physical synthesis of large ASICs
Ruchir Puri, David S. Kung, Anthony D. Drumm
GLVLSI
2002
IEEE
107views VLSI» more  GLVLSI 2002»
10 years 4 months ago
Multi-voltage low power convolvers using the polynomial residue number system
Vassilis Paliouras, Alexander Skavantzos, Thanos S...
GLVLSI
2002
IEEE
109views VLSI» more  GLVLSI 2002»
10 years 4 months ago
Minimizing resources in a repeating schedule for a split-node data-flow graph
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
Timothy W. O'Neil, Edwin Hsing-Mean Sha
GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
10 years 4 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
GLVLSI
2002
IEEE
94views VLSI» more  GLVLSI 2002»
10 years 4 months ago
Properties of on-chip inductive current loops
Andrey V. Mezhiba, Eby G. Friedman
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