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GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
9 years 6 months ago
Increasing design space of the instruction queue with tag coding
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
Junwei Zhou, Andrew Mason
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
9 years 6 months ago
VLSI CAD tool protection by birthmarking design solutions
Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern...
Lin Yuan, Gang Qu, Ankur Srivastava
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
9 years 6 months ago
Interconnect capacitance extraction for system LCD circuits
This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI ...
Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimot...
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
9 years 6 months ago
PIM lite: a multithreaded processor-in-memory prototype
Abstract— PIM Lite is a processor-in-memory prototype implemented in a 0.18 micron logic process. PIM Lite provides a complete working demonstration of a minimal-state, lightweig...
Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinz...
GLVLSI
2005
IEEE
158views VLSI» more  GLVLSI 2005»
9 years 6 months ago
Quantum-dot cellular automata SPICE macro model
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
Rui Tang, Fengming Zhang, Yong-Bin Kim
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
9 years 6 months ago
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
Vishal Suthar, Shantanu Dutt
GLVLSI
2005
IEEE
133views VLSI» more  GLVLSI 2005»
9 years 6 months ago
Generating decision regions in analog measurement spaces
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
GLVLSI
2005
IEEE
110views VLSI» more  GLVLSI 2005»
9 years 6 months ago
QCA channel routing with wire crossing minimization
Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chemica...
Brian Stephen Smith, Sung Kyu Lim
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
9 years 6 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
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