GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Two generations of a wideband low noise amplifier (LNA) employing noise canceling principle have been synthesized. The first generation design was fabricated in a 0.35 µm SiGe Bi...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to high...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...