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GLVLSI
2007
IEEE
173views VLSI» more  GLVLSI 2007»
9 years 8 months ago
Modeling and estimating leakage current in series-parallel CMOS networks
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
Paulo F. Butzen, André Inácio Reis, ...
GLVLSI
2007
IEEE
186views VLSI» more  GLVLSI 2007»
9 years 8 months ago
Block placement to ensure channel routability
Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total widt...
Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghav...
GLVLSI
2007
IEEE
142views VLSI» more  GLVLSI 2007»
9 years 9 months ago
Three-valued automated reasoning on analog properties
Raffaella Gentilini, Klaus Schneider, Alexander Dr...
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
9 years 9 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
GLVLSI
2007
IEEE
153views VLSI» more  GLVLSI 2007»
9 years 9 months ago
Address generation for nanowire decoders
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
Jia Wang, Ming-Yang Kao, Hai Zhou
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
9 years 12 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
9 years 12 months ago
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
9 years 12 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
9 years 12 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
GLVLSI
2007
IEEE
126views VLSI» more  GLVLSI 2007»
9 years 12 months ago
An asynchronous fpga logic cell implementation
Atabak Mahram, Mehrdad Najibi, Hossein Pedram
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