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GLVLSI
2008
IEEE
169views VLSI» more  GLVLSI 2008»
13 years 3 months ago
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
13 years 3 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
13 years 3 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
GLVLSI
2008
IEEE
183views VLSI» more  GLVLSI 2008»
13 years 4 months ago
An analytical model for the upper bound on temperature differences on a chip
The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be u...
Shervin Sharifi, Tajana Simunic Rosing
GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
13 years 4 months ago
Guided test generation for isolation and detection of embedded trojans in ics
Mainak Banga, Maheshwar Chandrasekar, Lei Fang, Mi...
GLVLSI
2008
IEEE
105views VLSI» more  GLVLSI 2008»
13 years 4 months ago
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip
This paper presents a process variation tolerant, SoC ready, 1GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologie...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
GLVLSI
2008
IEEE
190views VLSI» more  GLVLSI 2008»
13 years 10 months ago
A low leakage 9t sram cell for ultra-low power operation
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
GLVLSI
2008
IEEE
128views VLSI» more  GLVLSI 2008»
13 years 10 months ago
NBTI-aware flip-flop characterization and design
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
Hamed Abrishami, Safar Hatami, Behnam Amelifard, M...
GLVLSI
2008
IEEE
137views VLSI» more  GLVLSI 2008»
13 years 10 months ago
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
Ann Gordon-Ross, Jeremy Lau, Brad Calder
GLVLSI
2008
IEEE
95views VLSI» more  GLVLSI 2008»
13 years 10 months ago
In-order pulsed charge recycling in off-chip data buses
This paper presents in-order pulsed charge recycling to reduce energy consumption in an off-chip data bus. The proposed technique performs charge recycling by employing three step...
Kimish Patel, Wonbok Lee, Massoud Pedram