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GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
GLVLSI
2010
IEEE
172views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Online convex optimization-based algorithm for thermal management of MPSoCs
Meeting the temperature constraints and reducing the hot-spots are critical for achieving reliable and efficient operation of complex multi-core systems. The goal of thermal mana...
Francesco Zanini, David Atienza, Giovanni De Miche...
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Read-out schemes for a CNTFET-based crossbar memory
This paper investigates read-out schemes for a crossbar memory using CNTFET-based elements as cross-points. Two read-out schemes are presented in this paper; the first scheme bias...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
GLVLSI
2010
IEEE
234views VLSI» more  GLVLSI 2010»
10 years 6 months ago
On-chip point-of-load voltage regulator for distributed power supplies
An ultra-low area, current efficient voltage regulator appropriate for distributed point-of-load voltage regulation in high performance integrated circuits (ICs) is described in t...
Selcuk Kose, Eby G. Friedman
GLVLSI
2010
IEEE
136views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Thermal-aware compilation for system-on-chip processing architectures
The development of compiler-based mechanisms to reduce the percentage of hotspots and optimize the thermal profile of large register files has become an important issue. Thermal...
Mohamed M. Sabry, José L. Ayala, David Atie...
GLVLSI
2010
IEEE
119views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Line width optimization for interdigitated power/ground networks
Higher operating frequencies have increased the importance of inductance in power and ground networks. The effective inductance of the power and ground network can be reduced with...
Renatas Jakushokas, Eby G. Friedman
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
10 years 6 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
10 years 6 months ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
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